不良研究所

From astronomy to Huygens' discovery of coupled oscillations to the electrical signals that drive the human heart, periodic motion has been fundamental in many fields within science and engineering. Indeed, its recurrent nature is essential in the operation of motors and AC power, and has applications in robotic autonomous vehicles, and biomedical engineering.
In this systems & control project, the student will learn and apply analytic and topological techniques to study the orbit structures of differential equations on configuration manifolds. In particular, energy based methods provide a comprehensive framework for characterizing closed orbits and for examining the stability of perturbed periodic trajectories of physical systems. This project includes the creation of computer simulations of biological and control systems exhibiting exhibiting periodicity.
Knowledge of manifold theory, non-linear dynamics and linear algebra is required.

Literature review of selected topics within dynamical systems and orbital dynamics 芒鈧�鈥� including Hamiltonian systems. Applications of the relevant analysis and design methods to specific examples in control and biological systems. Computer simulations of the corresponding systems' behaviour.

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Engineering is a challenging discipline and while engineering programs are designed to teach students the necessary technical knowledge and skills, as well as professional skills required to succeed, it is also important to teach them to cope with failure, e.g., to be less fearful of failure, to be resilient when faced with failure, to learn from failure, and to view failure as part of the learning, scientific, and engineering processes.

The SURE student will participate in the following:

1. Completing a literature review on failure in STEM disciplines with a specific focus on engineering.

2. Assisting to develop a mixed methods research approach (combination of quantitative date from surveys and qualitative data from structured interviews) to understand engineering students' perceptions of failure and the link between engineering identity and coping with听failure.

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To model the electromagnetic fields accurately and efficiently within sophisticated microstructures of modern engineering systems, devices, and biological structures, high performance computing (HPC) methods, such as parallel and distributed simulations on emerging multicore/manycore platforms, are deemed promising for overcoming current computational bottlenecks. While robust and reliable 3-D automatic mesh generation procedures and solution strategies for electromagnetics are emerging, major computational challenges still remain for effective parallel and distributed 3-D adaptive finite element methods (AFEMs). Uniting AFEMs and HPC methods to achieve high gains in efficiency makes it possible to solve previously intractable problems; however, effective implementation of such techniques is still not well understood. AFEMs for parallel/distributed computing introduce complications that do not arise with simpler solution strategies. For example, adaptive algorithms utilize unstructured meshes that make the task of balancing processor computational load more difficult than with uniform structures. To help address these challenges, machine learning (ML) based approaches will be leveraged for developing state-of-the-art mesh generation for complex systems including biomedical applications.

The students in this project will research and develop efficient ML-based parallel and distributed adaptive algorithms for unstructured meshes that use sophisticated data structures for implementing dynamic load balancing strategies for HPC environments such as multicore/manycore architectures. The students芒鈧�鈩� role will include involvement in all aspects of the engineering research process for this project including actual implementation of algorithms as executable code.

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In this on-going research project, we consider how to design a broadband wireless access communications system that can adaptably adjust itself to the continuously changing complex environment by using machine learning (ML) techniques. We aim to explore the potential of applying ML techniques to harvest relevant environmental information for improving the resource allocation, performance and operation of the corresponding broadband wireless access communications system. Relevant environmental information can include weather, terrain, propagation (e.g., power, frequencies, etc.), social relationships (e.g., user groups, social networks, etc.)
Various ML-based algorithms within a prototype testbed will be developed for the specific topics such as 3D channel modelling/estimation, hybrid ARQ, hybrid massive-MIMO precoding/beamforming, etc., to demonstrate the effectiveness of the Artificial Intelligence (AI)-augmented systems in terms of performance benchmarks such as energy consumption, increase in achievable capacity, reduction in interference, etc.
Students will have a chance to understand various new concepts and development tools in both wireless communications (channel modelling, antenna array, beam forming, MIMO, etc.) and machine learning (deep neural network, reinforcement leaning, etc.), and to be involved in practical prototype development, and testing. As an example, one sub-project aims to develop a learning mechanism to jointly the uplink and downlink beam directions in full-duplex mMIMO communication system. Other sub-project aims to make use of both the terrain and weather information available in many sources such as Google map, online meteo, to develop a ML-based channel estimator for dynamic resource allocation in a broadband wireless access communication system.

Study the general concepts of ML and wireless communications. Learn how to search for and read scientific papers on a given signal processing or machine learning methods. Investigate MATLAB toolboxes, PyTorch, Keras, Tensorflow, and DSP/FPGA hardware for possible applications to algorithm/prototype implementation. Assist in implementation and testing algorithms/prototypes, and in collecting, documenting and commenting on the test results. The following skills and experiences are great assets: software development/testing, antenna design, Matlab, Python, VHDL, etc.

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Full-Duplex Massive Multi-Input Multi-Output (FD-massive MIMO) Active Antennas Arrays (AAA) are considered for the next-generation broadband communications. Using a massive number of antenna elements can (i) help to adaptively create narrow beams continuously steered to follow the target user while avoiding interference from other users, (ii) increase the communications range, and system capacity. The smart AAA system can follow the mobile user based on (i) a hybrid 2-stage digital and RF precoding structure to reduce the complexity, and (ii) a full-duplex operation for simultaneous transmission/reception over a frequency slot to enhance both spectrum utilization and latency.
In this on-going project, we investigate, design and test new promising antenna 3-dimentional structures (such as metamaterials, EBG, dielectric filled, etc.), with integrated power and low noise amplifiers, as well as RF combiners/splitters and smart DSP based control sub-system. The hardware testbed consists of powerful multi-FPGA, multi-microprocessor, and RF Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) modules to be programmed with digital signal processing algorithms for transmission and reception/detection of real wireless communications signals.

Study the general concept of Full-Duplex massive MIMO, radio-wave propagation, antenna design and simulation; learn the operation of the antenna design and simulation CAD tools HFSS, Matlab, SystemVue, PCB/DSP/FPGA design tools; learn the operation of RF test equipment Vector Signal Generators, Signal/Spectrum Analyzers, VNAs; prepare the simulation and/or practical test set-ups; assist graduate students and/or research associates to design/test AAA sub-modules, and analyze simulation and/or test results.

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In the last 20 years, photonic integrated circuits have revolutionized several applications such as in communications and computing. The SURE project uses applied machine learning to design next-generation photonic integrated circuits enabling new device functions. Photonics brings the speed of light to applications such as high-performance quantum and neuromorphic computing, self-driving vehicles, biomedical sensors, and high-capacity data centers. The project will related to the design and experimental validation of new devices in silicon technology platform.

The qualified intern will join our听team in either creating a virtual听nanofabrication environment
using machine learning or validating design devices through experimental measurements and/or simulation. The role of the intern will be to help improve the performance and capabilities of new design methodologies. They will have a fundamental understanding of electronics/photonics, nanofabrication, programming (e.g., Python, JavaScript), and/or machine learning.

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The objective of this project is to understand the role of regularization in Markov games. One of the key conceptual challenges in Markov games is that Markov perfect equilibrium (MPE) is not unique and different MPE have different performance. Recent results in Markov decision processes (MDPs) suggest that one might be able to circumvent these challenges via regularization. The objective of this project is to combine the ideas of regularized MDPs with MPEs in Markov games.

1. Review the literature of regularized Markov decision processes, in particular the paper of Geist, Scherrer, and Pierquin, ICML 2019.

2. Review the literature on MPE in Markov games, in particular, the book by Filar and Vrieze.

3. Develop a dynamic programming algorithm to compute regularized MPE in Markov games.

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Neuromorphic systems aim to emulate the brain's architecture for advanced computing systems. Analog memory is a key component to store synaptic weights and support in-memory computation. Charge-trap transistors (CTTs) can be utilized as an area efficient analog memory. For versatility, most neuromorphic systems use an analog design approach, however, these topologies are prone to process, voltage, and temperature variations. To alleviate these issues, a digital design approach can be utilized. At the same time, digital designs tend to exhibit higher power consumption and design overhead. Designing a neuron requires, therefore, a good understanding of system limitations and trade-offs among different design approaches.
Typically, the leaky integrate-and-fire (LIF) model is used within neuromorphic computing systems. The LIF model, however, generally only supports a limited number of biological neuron behaviors due to the simplification of the underlying neural dynamics. This limited number of behaviors is acceptable for machine learning tasks, however, emerging and neuroscience-related applications require a higher level of bio-resemblance.

Objectives:
-Investigation and design of new neuron circuits with additional biological behaviors.
-Comparison of the designed analog and digital neuron circuits in terms of performance and scalability characteristics.
-Verification of the designed circuits as part of the CTT-based neuromorphic system.

Deliverables:
Deliverables for five phases of the project are as follows:
(1) Literature review (2 weeks): A minimum 3-page literature review of the state-of-the-art in this domain, particularly on different neuron design approaches.
(2) Design (10 weeks): Design analog and digital neuron circuits in Cadence Virtuoso using GlobalFoundries 22nm FDX FDSOI technology.
(3) Simulation and verification (2 Weeks): Simulate and verify the functionality of the designed circuits based on arbitrary input signals.
(4) Optimization (1 week): Optimize the designed circuit for power consumption, robustness, area, and variations (Monte Carlo simulations).
(5) Wrap-up Phase (1 week): Documentation and poster.

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Rather than designing large systems-on-chip (SoCs), the chip design community is shifting towards heterogeneous integration of small chiplets that are optimized for a specific function. The chiplet paradigm promotes cost-effectiveness, performance scalability, and shorter time-to-market. That said, significant challenges must be addressed to enable chiplet-based integration. These challenges include significant financial contribution and technological enhancement in terms of electronic design automation (EDA), system architecture, design methodologies, and electronic packaging.

The current prevailing approach involves dividing an SoC at the typical intellectual property (IP)-level (i.e., memory, compute cores, I/O interfaces, and voltage regulators). Nevertheless, the implications of partitioning an SoC into multiple chiplets, on performance, cost, and reliability across various abstraction levels have received less attention. The target of this project is to extract microarchitectural features for breaking down a monolithic design of various IPs within an SoC to develop new chiplet-based microarchitectures. We target three applications for the input SoCs: general-purpose processors, domain-specific accelerators, and non-von Neuman architectures (i.e., neuromorphic and in-memory computing approaches). The extracted microarchitectural features should consider circuit- and system-level implications in terms of performance, cost, and scalability. The extracted features should be compatible with graph-based representation to support reconstitution during the design space exploration stage (note that developing the reconstitution approach and design space exploration are not part of this project).

The tasks are as follows:

1) Review the literature for the three applications of interest and extract typical IPs for each application, identify performance metrics, and analyze recent chiplet-based architectures.
2) Extract microarchitectural features for breaking down a monolithic design with various IPs for each application and developing a dependency map between features in terms of performance, cost, and scalability.
3) Represent the extracted features using a compatible graph-based data structure.

Deliverables:

1) For Task 1: A comprehensive literature review
2) For Task 2: Theoretical expressions of the dependency between extracted features represented by a graph data structure
3) For Task 3: Combining the subgraphs from Task 2 and delivering them as a complete graph model

A prospective candidate is expected to have the following qualifications:

1) [Required] Basic knowledge of computer microarchitecture and preferably prior projects related to computer architecture
2) [Required] Familiarity with data structures and skills related to object-oriented programming, graphs, writing scripts, and debugging in Python [preferred], Java, or C++
3) [Required] Already taken or taking a basic computer architecture course (e.g., ECSE 425 or an online course with similar content)
4) [Preferred] Familiarity with basic graph algorithms (e.g., DFS and BFS)

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Three-dimensional (3D) integration is a promising platform to address the limitation of conventional systems-on-chip (SoCs) for performance scaling. In 3D integrated circuits (ICs), each layer can be independently fabricated using the optimal process and technology for the function on that layer, subsequently, the layers are stacked, and connections are formed using TSVs. As the semiconductor industry targets significantly higher power density for 3D ICs (above 1 W/mm2), novel power delivery methodologies for 3D ICs, including fully integrated power delivery methodology, are proposed. In integrated power delivery methodology, the last stage of power conversion is integrated on-chip leading to a significant reduction in power loss and voltage fluctuation at the load end. Employment of recently proposed integrated power delivery methodologies requires novel power management strategies that meet the restricted thermal constraints in 3D ICs.

Power management encompasses the implementation of hardware and software techniques to control, monitor, and optimize the distribution and consumption of electrical power in electronic systems, such as dynamic voltage and frequency scaling, clock gating, and advanced power gating mechanisms, as well as the utilization of sophisticated algorithms to dynamically adjust power states based on workload demands, aiming to achieve the highest operational efficiency while minimizing energy consumption. The objective of this project is to develop a co-design framework for a thermal-aware power management strategy that meets the specific requirements of integrated power delivery methodology in 3D ICs. We evaluate and benchmark various systems equipped with the proposed power management strategy in terms of power, performance, and reliability metrics.

The tasks are as follows:

1) Review the literature on the available power management techniques, especially those that consider the thermal factors, across various design abstraction levels.
2) Developing novel or adapting available techniques to meet the specific requirements of integrated power delivery, thermal management, and reliability in 3D ICs.
3) A thermal-aware power management co-design framework (preferably in Python language) that is equipped with several power management techniques for 3D ICs.
4) Benchmarking the developed techniques using standard tools (e.g., ARTSim, ArchFP, and Sniper) and benchmark suits (e.g., PARSEC and MCNC).
5) Hardware-level implementation of the proposed techniques (analog/digital).

Deliverables:

1) For Task 1: A comprehensive literature review, covering state-of-the-art algorithms, heuristics, and hardware-related techniques.
2) For Task 2: Theoretical modeling of each technique in terms of metrics of interest, such as total power consumption, max temperature, maximum operating frequency, and mean time to failure (MTTF). The models should be robust to support 3D ICs that employ integrated power delivery methodology.
3) For Task 3: The implemented code of the framework, relevant heuristics, and relevant expressions for estimating the time and space complexity.
4) For Task 4: benchmarking results, including a comparison to state-of-the-art previous works.
5) For Task 5: Analog or digital design results in standard format (e.g., GDSII and VHDL)

A prospective candidate is expected to have the following qualifications:

1) [Required] Advanced data structures and object-oriented programming skills, writing scripts, and debugging in Python [preferred], Java, or C++
2) [Preferred] Background knowledge or prior projects related to analog design, multi-objective optimization, machine learning, and/or heuristics.

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